Older CD-ROM optical disks are being replaced with high-capacity digital-versatile disk (DVD) optical disks for use on computer systems. DVD offers much higher data storage than CD-ROM. However, the higher data density ultimately requires that more data be sent from the DVD controller to a host such as a personal computer (PC's) host microprocessor or central processing unit.
Most PC's allow for expansion by plugging expansion or adapter cards into an expansion bus. The AT bus used in the original IBM-AT PC is still widely used for connecting peripheral devices such as modems and hard disk drives to the PC. The AT bus standard has been extended with the AT-Attachment with Packet Interface Extension (ATAPI) standard. ATAPI is often used for communicating with hard disks and other peripherals over the AT bus.
Peripheral devices often require device-specific control information such as a sector, track, or header ID to search for, or positioning information for a read head. This information could be transferred as individual writes to a register in the peripheral's AT adapter card, but the ATAPI specification is an improvement since this information is written as a single packet containing many bytes. The packet can be physically transferred using data-bursts rather than single write cycles. Bursts are more efficient of the host microprocessor and thus improve performance.
A communication session with a peripheral device using ATAPI proceeds through several phases. FIG. 1 shows phases in an ATAPI data transfer. The host microprocessor writes a command to a command register on the ATAPI peripheral during command phase 11. This may simply be a command to accept a packet of information about the actual operation being requested of the peripheral device. For such packet commands, packet phase 10 is entered where a multi-byte packet is written from the host to the peripheral device. The peripheral device then decodes this packet and executes the command indicated by the packet.
Frequently, the packet is a command for data transfer. Then data phase 12 is entered in which the data is transferred from the peripheral to the host. Standard 10 cycles or more efficient direct-memory access (DMA) cycles can be used for the data transfer. Typically a large block of data is transferred by specifying a starting address and a byte count. Once a transfer counter that was set to the byte count decrements to zero, the transfer is completed.
After the data transfer, status is reported to the host during status phase 14. An error could have occurred during the transfer, such as a data under-run where the peripheral was not able to fetch the data as quickly as the host received it. The wrong sector could have been read or data errors detected during the transfer. The host checks for these errors by reading a status register on the peripheral device.
The peripheral device generates an interrupt to the host microprocessor at various stages, such as when the data has been located and is ready for transfer. The host can also read the status register for busy, device ready, and data request status bits. Overlapped commands can be supported by the peripheral device going to release state 15 to release the AT bus for another command while the peripheral is getting itself set up. A service command is issued by the host to enter data phase 12 after a bus disconnect.
FIG. 2 shows task registers on an ATAPI peripheral device that are accessed by a host. Relatively few address locations are used by each peripheral device. The host indicates which register to access by setting an address using two chip-select signal CS3, CS1, and the three lowest address bits A2:0. When these bits are 10000, a data port is accessed for multi-byte transfers of data or a command packet. The data port can be connected to a first-in-first-out FIFO buffer that receives the packet or contains the data for transfer to the host.
An interrupt-reason register is accessed when the bits are 10010, while a tag byte is accessed for 10011. High and low 8-bit portions of a byte count of the transfer, and a drive select register are accessed using chip select/addresses 10100, 10101, and 10110. Other registers are different depending on whether the host is reading or writing. Address 10001 writes a feature register but reads an error status register. The command is written to address 10111 but a status is read from this address. Likewise, address 11110 writes device control but reads an alternate status register. All of these registers are 8-bits wide, except for the data port which is 16 bits wide.
Microcontroller on Peripheral Controls Transfers--FIG. 3
FIG. 3 shows an optical disk controller using a microcontroller for interfacing to a host using ATAPI. Optical disk 18 has a read head that is positioned by servo 32. Data is read from optical disk 18 into buffer 30, where error corrector 28 performs error correction on the data. Corrected data is transferred to FIFO 22 for reading by the host using AT bus 40.
The host writes command packets to FIFO 22 by first writing a packet-write command to task registers 24. Task registers 24 were shown in FIG. 2. Microcontroller 20 reads the packet-write command from task registers 24 and sets up FIFO 22 to receive the command packet from the host. Then microcontroller 20 decodes the command packet in FIFO 22 and executes the task. For data transfers, microcontroller must first position the read head by commanding servo 32 to move to the desired position, then operating with error corrector 28 to correct the data read from optical disk 18. The corrected data must be transferred by microcontroller 20 from buffer 30 to FIFO 22 each time FIFO 22 empties out. Microcontroller 20 notifies the host by sending interrupt 38 to the host and by setting bus status bits in bus signals 26. Microcontroller 20 must monitor FIFO 22 and refill it with data and also monitor handshaking with the host.
Such a microcontroller-based interface was effective for CD-ROM optical disks, since a relatively simple error correction was used and data rates were low. However, DVD optical disks use more complex error correction that requires more processing bandwidth from microcontroller 20. Higher data rates also increase the demands on microcontroller 20. Faster, more expensive microcontrollers may be required.
Microcontrollers are programmed using well-known techniques. The machine-level instructions, or firmware code, is stored in a ROM, and may be modified if the ROM is programmable, as is EPROM or EEPROM memory. A microcontroller is a self-contained computer and can perform a very wide range of tasks, and can be easily modified. However, microcontrollers are relatively expensive, since a high level of integration is needed to have a CPU, RAM, ROM, and I/O all on the same silicon die.
At higher speeds, synchronization is also a problem. The microcontroller typically operates with its own clock, which is asynchronous to the AT bus. Metastability can occur when the microcontroller reads or writes AT-bus signals. Metastable inputs and outputs can cause failures that are hard to reproduce or detect.
What is desired is a host interface for a DVD optical-disk controller. It is desired to reduce the loading of the microcontroller by the host interface, to free microcontroller bandwidth for DVD error correction. It is further desired to eliminate meta-stability problems from the AT bus interface. A host interface for the higher data requirements of DVD is desired.